State-of-the-art metal-oxide-semiconductor field effect transistors require shrinking the gate length below 0.25 .mu.m. The standard process for forming the gates is by depositing a polysilicon layer, etching this layer to define the required gate length, and using the polysilicon as a mask for the source/drain shallow implant step. The shallow implant step is followed by forming a nitride sidewall spacer, implanting the deep ohmic region in the source/drain and then forming a metal silicide to the gate and the source/drain implant. The resistance of the gate thus increases as the gate length is reduced, because the gate metal silicide has the same gate length as the polysilicon gate underneath. The gate resistance slows down the devices because of the RC time delay. Alternatively, one can form a metal gate which is longer than the polysilicon gate by opening a window in an oxide layer and patterning metal. This process has produced the fastest silicon devices to date, but requires a highly critical realignment to the initial polysilicon gate, which if not successful, would result in shorting the gate with the ohmic source/drain contacts. Therefore the above process is not compatible with manufacturing.
In addition to an increase in gate resistance due to scaling down the gate length in MOS FET'S, the ohmic source/drain contacts formed by ion implantation cannot be scaled in depth as required to keep the aspect ratio of gate length to junction depth greater than 1. As the gate length of the MOS FET's are scaled to smaller dimensions, the resistance of the ohmic regions increases, which degrades the speed performance of the FETS. The threshold voltage has to be adjusted by a channel implant, which has to become shallower in order to prevent short channel effects. The shallower implant, in turn, reduces the carrier mobility in the inversion layer, and is also becoming more difficult to control.